Part Number Hot Search : 
SOE339 CD7642CP N7000 1N5744A AD843SH XXXGX T7700 54HC27
Product Description
Full Text Search
 

To Download M830 Datasheet File

  If you can't view the Datasheet, Please click here to try to view without PDF Reader .  
 
 


  Datasheet File OCR Text:
 Micro Networks
An Integrated Circuit Systems Company
M830 Series
Preliminary Specifications
M830 Series
12.249Gb/s OC-192 Clock & Data Recovery Transmitter Module
DESCRIPTION
The M830 Series CDR module is specifically designed to regenerate the spectral clock component from an incoming NRZ data stream, incorporating forward error correction, and output a low-jitter clock and retimed complementary data. The module utilizes a phase-locked loop architecture incorporating a high-stability, low noise SAW VCO to provide extremely low jitter clock and data outputs. The incoming data is frequency doubled to recover the clock component. The clock signal is then filtered by a microwave band pass filter to remove wide band noise and spurious signal. This signal is further filtered using the narrow band SAW VCO based PLL to minimize the noise close to the carrier. The low jitter clock is then used to retime the data and serves as the module's clock output. The module provides usercontrolled clock phase shifter and output data crossover adjustments to optimize system performance. PLL lock-in range and loop transfer characteristics are optimized for minimal jitter in accordance with ITU and Bellcore standards for SONET/SDH systems.
FEATURES
Superior PLL-based jitter performance 8psec p-p jitter 0.9Vp-p complementary data outputs 1 Ul externally adjustable clock phase 200mVp-p input sensitivity Optional adjustable bias @ data input to decision circuit Externally adjustable decision threshold
APPLICATIONS
ABSOLUTE MAX RATINGS Operating Temp. Range (Case) ............................. 0C to +70C Storage Temp. Range (Ambient) ..................... -40C to +125C Power Supply Voltage Vcc: ...................................................... +5.25Vdc Vee: ...................................................... -5.25Vdc Ref Voltage ....................................................... +0.3 to -1.6V Phase Shift Control .....................................................0 to +15V
SONET OC-192 and SDH STM Physical Layer and Clock and Data Recovery Applications Incorporating Forward Error Correction
ISO 9001 Registered
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
fax: 508-852-8456
www.micronetworks.com
Micro Networks
An Integrated Circuit Systems Company SPECIFICATIONS
M830 Series
Preliminary Specifications
Specifications @ Vcc = +5.0 Volts, Vee = -5.0 Volts, Data in = 231-1 PRBS NRZ, Mark ratio = 1:2, and TA = +25C unless otherwise specified PARAMETER Min Typ Max Units Condition
Data Rate Data Input Level Data Input Return Loss Data Output Voltage Data Output Jitter Data Output Duty Cycle Distortion Data Output Rise Time (20% to 80%) Data Output Fall Time (80% to 20%) Data Output Return Loss PLL Loop BW Decision Threshold Control Decision Threshold Control Voltage Range Clock Output Level Clock Phase Control Clock Phase Control Voltage Clock SSB Phase Noise @100Hz Offset @1kHz Offset @10kHz Offset Clock Jitter Spurious Output Harmonic Output Supply Voltage Vcc Vee Supply Current Icc Iee +4.75 -5.25 -0.75 800 1 0 10 10 750 200
12.2493 600 10 900 7.5 2.5 25 25 12 .3 90 12 1100 10 5 35 35
Gb/s mVp-p dB mVp-p psec p-p % psec psec dB MHz %
NRZ Single-ended, 50, AC coupled 50MHz to 7GHz Data & Data 27-1 PRBS NRZ 50, AC coupled 50, AC coupled 50MHz to 9GHz Relative to max Data Input Voltage Ref -0.2 to -0.75V
-0.2 1200 1400 +15 -70 -85 -90 7.5 -50 -30 +5.0 -5.0 450 300 +5.25 -4.75 600 550 9
Volts mVp-p UI Volts dBc/Hz dBc/Hz dBc/Hz psec p-p dBc dBc Volts Volts mA mA
Internal load of 45 to -0.45V 50, AC coupled 10k, minimum load impedance 231-1 PRBS NRZ
27-1 PRBS NRZ
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
fax: 508-852-8456
www.micronetworks.com
Micro Networks
An Integrated Circuit Systems Company BLOCK DIAGRAM
M830 Series
Preliminary Specifications
The M830 clock and data recovery module has a SAW VCO based phase-locked loop architecture. The 1.225GHz fundamental VCO is implemented as a transmission oscillator. The oscillator loop includes the SAW resonator that has a linear phase with frequency characteristic, a linear voltage controlled phase shifter, loop amplifier, and power divider to couple signal from the loop. The oscillator is frequency doubled to 2.450GHz and band pass filtered. The 2.450GHz is then multiplied by five to the final frequency of 12.25GHz. The output of the VCO is power divided to provide an input to the phase detector and a clock signal. The input data is power divided to provide inputs to the decision circuit and the clock recovery circuitry. The input to the clock recovery circuit is amplified and applied to an analog frequency doubler to extract a clock spectral component from the NRZ data input stream. The 12.25GHz doubler output is band pass filtered and amplified. One VCO output and the clock extracted from the input data serve as inputs to a microwave phase detector. The phase detector output is applied to an
integrator circuit. The integrator output controls the phase shifter in the SAW VCO, completing the phaselock loop. The phase-locked loop causes the low noise VCO output to be phase-locked to the clock signal extracted from the NRZ input data, providing a low jitter clock signal. The clock signal is applied to a phase shifter that allows the timing between the input data and clock to be adjusted for optimum performance. The phase shifter output is amplified and band pass filtered to provide a low jitter and low spurious clock. The clock is power divided to provide the clock output of the module and the clock input to the decision circuit. The decision circuit is a high speed D flip-flop. In addition to the clock and data inputs, a user adjustable decision threshold voltage is available. This voltage is used to optimize the retimed data. The CDR threshold and phase shifter do not require adjustment over the temperature and input data level ranges. The clock output of the CDR is a low spurious sinusoidal signal and the complementary data outputs are AC coupled ECL signals. DC coupled ECL compatible data outputs are available.
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
fax: 508-852-8456
www.micronetworks.com
Micro Networks
An Integrated Circuit Systems Company DATA OUTPUT EYE DIAGRAM
M830 Series
Preliminary Specifications
Data Output Eye Diagram
CLOCK SPECTRUM
Narrow Band Clock Spectrum
Wide Band Clock Output Spectrum
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
fax: 508-852-8456
www.micronetworks.com
Micro Networks
An Integrated Circuit Systems Company ORDERING INFORMATION & MECHANICAL DIMENSIONS PIN DESCRIPTIONS
Part Number: Series No of Inputs D = Single Input Frequency Temperature Range K = 0 to +70C Package Type C = Case/Module Package REF LOC DEC +5V -5V GND PHASE ADJ DATA OUT CLK OUT M830 X XXXXX.XX X X Symbol DATA IN DATA OUT Name Data Input Data Output (non-inverted) Data Output (inverted) Clock Output (sinusoidal) Phase Shift Adjust Decision Threshold Adjustment Lock Detect +5V Power Supply -5V Power Supply Power Supply Ground Connection
2.49 [63.3] MAX
M830 Series
Preliminary Specifications
Description AC coupled 50 data input AC coupled 50 data output AC coupled 50 data output AC coupled 50 clock output User input to phase shift the recovered clock over a 100ps range. The control voltage range is 0 to 15V. User input to adjust the decision circuit threshold. The control range is -0.2V to -0.75V. TTL output indicating PLL loss of lock. TTL "1" indicates lock. TTL "0" indicates loss of lock. Positive power supply input. Negative power supply input. Ground lug to allow connection of power supply returns to case ground.
1.89 [48.0] MAX
DEC +5V -5V PHASE LOC ADJ REF -5V
DATA IN
2X 1.675 [42.54]
DATA OUT
DATA OUT
CLK OUT
2X .100 [2.54]
4X O .128-.134 THRU 2X .100 [O 3.25-3.40] [2.54] MOUNTING HOLES
2X LABEL 2X 2.275 [57.79]
.125 [3.18] MAX
6X .28 [7.1] 6X O .03 [E".76]
DEC +5V -5V PHASE LOC ADJ REF -5V
FL HD SCR'S REF 6X .03 [.76] REF 4X SMA CONN 1.45 [36.8]
.27 [6.8]
.62 [15.7] .18 [4.6] .23 [5.84] .39 [9.8] .43 [10.9] .27 [6.8] .29 [7.4]
.76 [19.3] MAX
.55 [14.0]
1.20 [30.5]
.54 [13.8]
.95 [24.1] 1.47 [37.4]
.36 [9.1]
.29 [7.4]
Micro Networks makes no assertion or warranty that the circuitry and the uses thereof disclosed herein are non-infringing on any valid US or foreign patents. Micro Networks assumes no liability as a result of the use of said specifications and reserves the right to make changes to specifications without notice. Contact your nearest Micro Networks sales representative office for the latest specifications.
Micro Networks
An Integrated Circuit Systems Company 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456
European Sales Headquarters Hertogsingel 20 6214 AD Maastricht The Netherlands tel: +31-43-32-70912 fax: +31-43-32-70715 Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com www.micronetworks.com
Rev. 15.0
Micro Networks
An Integrated Circuit Systems Company
Micro Networks Corporation
Worldwide Headquarters 324 Clark Street Worcester, MA 01606 USA tel: 508-852-5400 fax: 508-852-8456 European Sales Headquarters Hertogsingel 20 6214 AD Maastricht The Netherlands tel: +31-43-32-70912 fax: +31-43-32-70715
www.micronetworks.com


▲Up To Search▲   

 
Price & Availability of M830

All Rights Reserved © IC-ON-LINE 2003 - 2022  

[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]


 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X